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Disambiguation of "Soudris, Dimitrios"

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A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.

, , , , , and . DATE, page 946-947. IEEE Computer Society, (2005)

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Dimitrios Tsoutsoulopoulos University of Stuttgart

Dimitrios Thalassinos University of Stuttgart

 

Other publications of authors with the same name

A Novel Division Algorithm and Architectures for Parallel and Sequential Processing., , , and . Journal of Circuits, Systems, and Computers, 14 (2): 281-296 (2005)A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures., , and . Journal of Circuits, Systems, and Computers, 19 (3): 701-717 (2010)A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs., and . J. Low Power Electronics, 4 (3): 275-289 (2008)Systematic methodology for designing low power direct digital frequency synthesisers., , , and . IET Circuits, Devices & Systems, 1 (4): 293-304 (2007)A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck., , , , , and . IEEE Trans. VLSI Syst., 14 (3): 279-291 (2006)A Methodology for Alleviating the Performance Degradation of TMR Solutions., and . Embedded Systems Letters, 2 (4): 111-114 (2010)On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal., , , and . ISCAS (4), page 334-337. IEEE, (2001)A reusable IP FFT core for DSP applications., , , , , , and . ISCAS (3), page 621-624. IEEE, (2004)Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations., , , , and . ICICDT, page 1-4. IEEE, (2014)Accuracy of Quasi-Monte Carlo technique in failure probability estimations., , , , and . ICICDT, page 1-4. IEEE, (2016)