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Disambiguation of "Hameed, Fazal"

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Dynamic cache management in multi-core architectures through run-time adaptation.

, , and . DATE, page 485-490. IEEE, (2012)

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Other publications of authors with the same name

Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (4): 651-664 (2016)Dynamic thermal management in 3D multi-core architecture through run-time adaptation., , and . DATE, page 299-304. IEEE, (2011)Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores., , and . DATE, page 77-82. EDA Consortium San Jose, CA, USA / ACM DL, (2013)ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0., , , , and . CoRR, (2019)Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture., , and . DAC, page 37:1-37:6. ACM, (2014)A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement., and . IEEE Trans. VLSI Syst., 27 (10): 2375-2386 (2019)Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories., , , and . ACM Trans. Embed. Comput. Syst., 19 (6): 44:1-44:26 (2020)Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache., , and . CODES+ISSS, page 1:1-1:8. IEEE, (2013)Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches., , , , , and . ISLPED, page 236-241. ACM, (2016)Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads., , , and . LCTES, page 5-18. ACM, (2019)