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Design challenges for prototypical and emerging memory concepts relying on resistance switching., , , , and . CICC, page 1-7. IEEE, (2011)Stochastic Computing for Hardware Implementation of Binarized Neural Networks., , , , , and . CoRR, (2019)Analytical study of complementary memristive synchronous logic gates., , , , , , , , , and 3 other author(s). NANOARCH, page 70-75. IEEE Computer Society, (2013)Degenerate Kalman Filter Error Covariances and Their Convergence onto the Unstable Subspace., , , , , and . SIAM/ASA J. Uncertain. Quantification, 5 (1): 304-333 (2017)Memory-Centric Neuromorphic Computing With Nanodevices., , , , , , , , , and . BioCAS, page 1-4. IEEE, (2019)Crossbar architecture based on 2R complementary resistive switching memory cell., , , , , , , , , and 2 other author(s). NANOARCH, page 85-92. ACM, (2012)Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues., , , , , , , , and . IOLTS, page 243-244. IEEE, (2018)SPICE level analysis of Single Event Effects in an OxRRAM cell., , , , , and . LATW, page 1-5. IEEE Computer Society, (2013)A novel test structure for OxRRAM process variability evaluation., , , , and . Microelectronics Reliability, 53 (9-11): 1208-1212 (2013)Multilevel operation in oxide based resistive RAM with SET voltage modulation., , , , , and . DTIS, page 1-5. IEEE, (2016)