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Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis., , , , , and . J. Solid-State Circuits, 45 (11): 2321-2329 (2010)Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC., , , , and . IEEE Trans. Circuits Syst. Video Techn., 17 (5): 568-577 (2007)Mapping Scalable Video Coding decoder on multi-core stream processors., , , , and . PCS, page 1-4. IEEE, (2009)Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices., , , , and . IEEE Trans. Circuits Syst. Video Techn., 19 (8): 1118-1128 (2009)Brain-Inspired Framework for Fusion of Multiple Depth Cues., , , , , , and . IEEE Trans. Circuits Syst. Video Techn., 23 (7): 1137-1149 (2013)Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder., , , , and . Signal Processing Systems, 50 (1): 1-17 (2008)Tera-scale performance machine learning SoC with dual stream processor architecture for multimedia content analysis., , , , , and . CICC, page 491-494. IEEE, (2009)Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC., , , and . ICASSP (3), page 900-903. IEEE, (2006)Steadiface: Real-Time Face-Centric Stabilization On Mobile Phones., , , and . ICIP, page 4599-4603. IEEE, (2019)Encoder Hardware Architecture for HEVC., , and . High Efficiency Video Coding, Springer, (2014)