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Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design., , , and . ISCAS (4), page 33-36. IEEE, (2001)An area-efficient versatile Reed-Solomon decoder for ADSL., , , and . ISCAS (1), page 517-520. IEEE, (1999)VLSI architecture of extended in-place path metric update for Viterbi decoders., , , and . ISCAS (4), page 206-209. IEEE, (2001)High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)., , , and . IEEE Trans. Computers, 53 (3): 375-380 (2004)VLSI architectural design tradeoffs for sliding-window log-MAP decoders., , , , and . IEEE Trans. VLSI Syst., 13 (4): 439-447 (2005)An area-efficient systolic division circuit over GF(2/sup m/) for secure communication., , , and . ISCAS (5), page 733-736. IEEE, (2002)VLSI architecture exploration for sliding-window Log-MAP decoders., , , , , and . ISCAS (2), page 513-516. IEEE, (2004)Memory arrangements in turbo decoders using sliding-window BCJR algorithm., , and . ISCAS (5), page 557-560. IEEE, (2002)An efficient approach for in-place scheduling of path metric update in Viterbi decoders., , , and . ISCAS, page 61-64. IEEE, (2000)Perceptual multi-cues 2D-to-3D conversion system., , , and . VCIP, page 1. IEEE, (2011)