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Disambiguation of "Karandikar, Shrirang K."

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The nuts and bolts of physical synthesis.

, , , , , , , , and . SLIP, page 89-94. ACM, (2007)

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K. Stahl

K. Gaiser

K. Lindow

Grzegorz K. Karch

Dipl.-Ing. Thomas Kuestner

Scan time reduction in DWI of the pancreas using simultaneous multislice technique with different acceleration factors: how fast can we go?, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)
 

Other publications of authors with the same name

Fast estimation of area-delay trade-offs in circuit sizing., and . ISCAS (4), page 3575-3578. IEEE, (2005)Logical effort based technology mapping., and . ICCAD, page 419-422. IEEE Computer Society / ACM, (2004)Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (1): 45-58 (2008)Fast Algorithms for Slew-Constrained Minimum Cost Buffering., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (11): 2009-2022 (2007)The nuts and bolts of physical synthesis., , , , , , , , and . SLIP, page 89-94. ACM, (2007)Fast algorithms for slew constrained minimum cost buffering., , , , , , and . DAC, page 308-313. ACM, (2006)Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect., and . DAC, page 377-382. ACM, (2001)Fast Comparisons of Circuit Implementations., and . DATE, page 910-915. IEEE Computer Society, (2004)FIRA - a novel method for benchmarking the cache hierarchy., , and . COMPUTE, page 14. ACM, (2012)Fast Electrical Correction Using Resizing and Buffering., , , , , and . ASP-DAC, page 553-558. IEEE Computer Society, (2007)