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A Flexible Design Flow for Software IP Binding in FPGA.

, , and . IEEE Trans. Industrial Informatics, 6 (4): 719-728 (2010)

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From Statistics to Circuits: Foundations for Future Physical Unclonable Functions., , , , , and . Towards Hardware-Intrinsic Security, Springer, (2010)The Impact of Aging on an FPGA-Based Physical Unclonable Function., , and . FPL, page 151-156. IEEE Computer Society, (2011)Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators., and . FPL, page 703-707. IEEE, (2009)An Analysis of Delay Based PUF Implementations on FPGA., , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 382-387. Springer, (2010)Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive., and . J. Cryptology, 24 (2): 375-397 (2011)Impact and compensation of correlated process variation on ring oscillator based puf., and . FPGA, page 285. ACM, (2009)A flexible design flow for software IP binding in commodity FPGA., , and . SIES, page 211-218. IEEE, (2009)Verifying information flow properties of firmware using symbolic execution., , , , and . DATE, page 337-342. IEEE, (2016)Physical unclonable function and true random number generator: a compact and scalable implementation., , , and . ACM Great Lakes Symposium on VLSI, page 425-428. ACM, (2009)A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions., , and . IACR Cryptology ePrint Archive, (2011)