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Disambiguation of "Tanakamaru, Shuhei"

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Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths.

, , , and . IEICE Transactions, 99-C (4): 444-451 (2016)

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Other publications of authors with the same name

Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs)., , and . J. Solid-State Circuits, 48 (11): 2920-2933 (2013)95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm., , , , , and . ISSCC, page 204-206. IEEE, (2011)Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme., , and . ASP-DAC, page 83-84. IEEE, (2013)Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory., , , , , , , and . J. Solid-State Circuits, 51 (8): 1938-1951 (2016)Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths., , , and . IEICE Transactions, 99-C (4): 444-451 (2016)Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten., , and . VLSIC, page 130-. IEEE, (2015)Reliability enhancement of 1Xnm TLC for cold flash and millennium memories., , , , , and . VLSIC, page 112-. IEEE, (2015)Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme., , and . ISSCC, page 424-426. IEEE, (2012)Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications., , and . ISSCC, page 226-227. IEEE, (2013)Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor., , , , and . CICC, page 1-4. IEEE, (2010)