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Disambiguation of "Lee, Chiou-Yng"

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Low-Complexity Digit-Serial Multiplier Over $GF(2^m)$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition.

, , , and . IEEE Trans. VLSI Syst., 25 (2): 735-746 (2017)

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Moosung Lee University of Stuttgart

Dongwon Lee University of Stuttgart

Junghwa Lee University of Stuttgart

Ph. D. Benjamin Lee University of Stuttgart

Yoonhee Lee University of Stuttgart

 

Other publications of authors with the same name

Unified Parallel Systolic Multiplier Over GF(2m)., , , and . J. Comput. Sci. Technol., 22 (1): 28-38 (2007)Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation., , and . J. Comput. Sci. Technol., 21 (6): 887-892 (2006)Efficient $M$ -ary Exponentiation over $GF(2^m)$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier., , and . IEEE Trans. on Circuits and Systems, 61-I (11): 3125-3134 (2014)Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m).. Integration, 43 (1): 113-123 (2010)Low-Complexity Parallel Systolic Montgomery Multipliers over GF(2m) Using Toeplitz Matrix-Vector Representation.. IEICE Transactions, 91-A (6): 1470-1477 (2008)Subquadratic Space-Complexity Parallel Systolic Multiplier Based on Karatsuba Algorithm and Block Recombination., , and . ICGEC (2), volume 388 of Advances in Intelligent Systems and Computing, page 187-200. Springer, (2015)New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm., , and . APCCAS, page 610-613. IEEE, (2006)Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach., , and . IEEE Trans. VLSI Syst., 24 (7): 2413-2425 (2016)New bit-parallel systolic multipliers for a class of GF(2m)., , and . ISCAS (4), page 578-581. IEEE, (2001)Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm"., and . IEEE Trans. on Circuits and Systems, 63-I (8): 1316-1319 (2016)