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Disambiguation of "Azevedo, Arnaldo"

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Analysis of video filtering on the cell processor.

, , , , and . ISCAS, page 488-491. IEEE, (2008)

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Other publications of authors with the same name

A Multidimensional Software Cache for Scratchpad-Based Systems., and . IJERTCS, 1 (4): 1-20 (2010)Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow., , , , , , , , , and 2 other author(s). SIGBED Review, 10 (3): 23-34 (2013)When reconfigurable architecture meets network-on-chip., , and . SBCCI, page 216-221. ACM, (2004)MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV., , , and . ISCAS, page 1617-1620. IEEE, (2007)Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units., , , and . IEEE International Workshop on Rapid System Prototyping, page 255-257. IEEE Computer Society, (2005)Scalability of Macroblock-level Parallelism for H.264 Decoding., , , , , and . ICPADS, page 236-243. IEEE Computer Society, (2009)A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile., , , , , and . J. Real-Time Image Processing, 8 (1): 127-140 (2013)Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV., , , and . VLSI-SoC, page 52-57. IEEE, (2006)FPGA Prototyping Strategy for a H.264/AVC Video Decoder., , , , , , , and . IEEE International Workshop on Rapid System Prototyping, page 174-180. IEEE Computer Society, (2007)FPGA Design of A H.264/AVC Main Profile Decoder for HDTV., , , , , , and . FPL, page 1-6. IEEE, (2006)