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On the use of GP-GPUs for accelerating compute-intensive EDA applications.

, , , , , , and . DATE, page 1357-1366. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Addressing verification challenges of heterogeneous systems based on IBM POWER9., , , , , , , , , and 1 other author(s). IBM Journal of Research and Development, 62 (4/5): 11 (2018)Gate-Level Simulation with GPU Computing., , and . ACM Trans. Design Autom. Electr. Syst., 16 (3): 30:1-30:26 (2011)SystemC simulation on GP-GPUs: CUDA vs. OpenCL., , , and . CODES+ISSS, page 343-352. ACM, (2012)Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms., , , , , , , and . ICCAD, page 311-317. IEEE, (2013)GCS: High-performance gate-level simulation with GPGPUs., , and . DATE, page 1332-1337. IEEE, (2009)Activity-based refinement for abstraction-guided simulation., and . HLDVT, page 146-153. IEEE Computer Society, (2009)Checking architectural outputs instruction-by-instruction on acceleration platforms., , , , and . DAC, page 955-961. ACM, (2012)EQUIPE: Parallel equivalence checking with GP-GPUs., and . ICCD, page 486-493. IEEE Computer Society, (2010)ArChiVED: Architectural checking via event digests for high performance validation., , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Approximating checkers for simulation acceleration., , , , , , and . DATE, page 153-158. IEEE, (2012)