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Disambiguation of "Ciobanu, Catalin Bogdan"

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The SARC Architecture.

, , , , , , , , , and . IEEE Micro, 30 (5): 16-29 (2010)

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Other publications of authors with the same name

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project., , , , , , , , and . ISVLSI, page 368-373. IEEE Computer Society, (2017)Separable 2D Convolution with Polymorphic Register Files., and . ARCS, volume 7767 of Lecture Notes in Computer Science, page 317-328. Springer, (2013)FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration., , , , , , , , , and 11 other author(s). Microprocessors and Microsystems - Embedded Hardware Design, 39 (4-5): 321-338 (2015)The Case for Polymorphic Registers in Dataflow Computing., , , and . International Journal of Parallel Programming, 46 (6): 1185-1219 (2018)MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs., , , and . IPDPS Workshops, page 107-114. IEEE Computer Society, (2018)EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing., , , , , , , , , and 7 other author(s). CSE, page 339-342. IEEE Computer Society, (2015)Real-Time Olivary Neuron Simulations on Dataflow Computing Machines., , , , , , and . ISC, volume 8488 of Lecture Notes in Computer Science, page 487-497. Springer, (2014)Dataflow computing with Polymorphic Registers., , , and . ICSAMOS, page 314-321. IEEE, (2013)HLS Support for Polymorphic Parallel Memories., , , , , , and . VLSI-SoC, page 143-148. IEEE, (2018)Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS., , , , , , and . VLSI-SoC (Selected Papers), volume 561 of IFIP Advances in Information and Communication Technology, page 53-78. Springer, (2018)