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Netbench: Framework for Evaluation of Packet Processing Algorithms.

, , , , and . ANCS, page 95-96. IEEE Computer Society, (2011)

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Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing., , and . DSD, page 823-829. IEEE Computer Society, (2009)Mapping Trained Neural Networks to FPNNs., , and . DDECS, page 157-160. IEEE Computer Society, (2015)Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration., , and . DSD, page 365-372. IEEE Computer Society, (2010)Fault tolerant system design and SEU injection based testing., , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (2): 155-173 (2013)High speed pattern matching algorithm based on deterministic finite automata with faulty transition table., and . ANCS, page 7. ACM, (2010)Netbench: Framework for Evaluation of Packet Processing Algorithms., , , , and . ANCS, page 95-96. IEEE Computer Society, (2011)Hardware architecture for the fast pattern matching., , and . DDECS, page 120-123. IEEE Computer Society, (2013)Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing., and . DDECS, page 149-152. IEEE Computer Society, (2010)Automatic Construction of On-line Checking Circuits Based on Finite Automata., , and . DSD, page 326-332. IEEE Computer Society, (2014)Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA., , , and . DSD, page 250-257. IEEE Computer Society, (2012)