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Disambiguation of "Ravindran, Rajiv A."

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Increasing the number of effective registers in a low-power processor using a windowed register file.

, , , , , , and . CASES, page 125-136. ACM, (2003)

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Other publications of authors with the same name

Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor., , , , , , and . IEEE Trans. Computers, 54 (8): 998-1012 (2005)Retargetable Cache Simulation Using High Level Processor Models., and . ACSAC, page 114-129. IEEE Computer Society, (2001)Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors., , , and . IEEE Micro, 24 (3): 10-20 (2004)Bitwidth cognizant architecture synthesis of custom hardwareaccelerators., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (11): 1355-1371 (2001)FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths., , , , , and . CGO, page 201-212. IEEE Computer Society, (2004)Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures., , and . MICRO, page 369-380. IEEE Computer Society, (2007)Compiler-managed partitioned data caches for low power., , and . LCTES, page 237-247. ACM, (2007)Increasing the number of effective registers in a low-power processor using a windowed register file., , , , , , and . CASES, page 125-136. ACM, (2003)Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache., , , , , , and . CGO, page 179-190. IEEE Computer Society, (2005)Systematic Register Bypass Customization for Application-Specific Processors., , , , , , and . ASAP, page 64-74. IEEE Computer Society, (2003)