Post-silicon validation is a crucial yet challenging problem primarily due to the increasing complexity of the semi-conductor value chain. Existing techniques cannot keep up with the rapid increase in the complexity of designs. Therefore, post-silicon validation is becoming an expensive bottleneck. Robust performance tuning is relevant to compensate impacts of process variations and non-ideal design implementations. We propose a novel approach based on Deep Reinforcement Learning and Learn to Optimize. The method automatically learns flexible tuning strategies tailored to specific circuits. Additionally, it addresses high-dimensional tuning tasks, including mixed data types and dependencies, e.g., on operating conditions. In this work, we introduce Learn to Tune and demonstrate its appealing properties in post-silicon validation, e.g., lower computational cost or faster time-to-optimize, allowing a more efficient adaption of the tuning to changing tuning conditions than classical methods.
Description
Learn to Tune: Robust Performance Tuning in Post-Silicon Validation | IEEE Conference Publication | IEEE Xplore
%0 Conference Paper
%1 10174123
%A Domanski, Peter
%A Pflüger, Dirk
%A Latty, Raphaël
%B 2023 IEEE European Test Symposium (ETS)
%D 2023
%K myown
%P 1-4
%R 10.1109/ETS56758.2023.10174123
%T Learn to Tune: Robust Performance Tuning in Post-Silicon Validation
%X Post-silicon validation is a crucial yet challenging problem primarily due to the increasing complexity of the semi-conductor value chain. Existing techniques cannot keep up with the rapid increase in the complexity of designs. Therefore, post-silicon validation is becoming an expensive bottleneck. Robust performance tuning is relevant to compensate impacts of process variations and non-ideal design implementations. We propose a novel approach based on Deep Reinforcement Learning and Learn to Optimize. The method automatically learns flexible tuning strategies tailored to specific circuits. Additionally, it addresses high-dimensional tuning tasks, including mixed data types and dependencies, e.g., on operating conditions. In this work, we introduce Learn to Tune and demonstrate its appealing properties in post-silicon validation, e.g., lower computational cost or faster time-to-optimize, allowing a more efficient adaption of the tuning to changing tuning conditions than classical methods.
@inproceedings{10174123,
abstract = {Post-silicon validation is a crucial yet challenging problem primarily due to the increasing complexity of the semi-conductor value chain. Existing techniques cannot keep up with the rapid increase in the complexity of designs. Therefore, post-silicon validation is becoming an expensive bottleneck. Robust performance tuning is relevant to compensate impacts of process variations and non-ideal design implementations. We propose a novel approach based on Deep Reinforcement Learning and Learn to Optimize. The method automatically learns flexible tuning strategies tailored to specific circuits. Additionally, it addresses high-dimensional tuning tasks, including mixed data types and dependencies, e.g., on operating conditions. In this work, we introduce Learn to Tune and demonstrate its appealing properties in post-silicon validation, e.g., lower computational cost or faster time-to-optimize, allowing a more efficient adaption of the tuning to changing tuning conditions than classical methods.},
added-at = {2023-10-19T16:32:18.000+0200},
author = {Domanski, Peter and Pflüger, Dirk and Latty, Raphaël},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2a65b51864b8efe845731417866ec6126/domanspr},
booktitle = {2023 IEEE European Test Symposium (ETS)},
description = {Learn to Tune: Robust Performance Tuning in Post-Silicon Validation | IEEE Conference Publication | IEEE Xplore},
doi = {10.1109/ETS56758.2023.10174123},
interhash = {d2c266786663d35ffd2060b34ec8ed8f},
intrahash = {a65b51864b8efe845731417866ec6126},
issn = {1558-1780},
keywords = {myown},
month = may,
pages = {1-4},
timestamp = {2023-10-19T16:32:18.000+0200},
title = {Learn to Tune: Robust Performance Tuning in Post-Silicon Validation},
year = 2023
}
