A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves a measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 1.62V supply. The measured dynamic range figure of merit is 174dB.
%0 Conference Paper
%1 4342711
%A Lee, J.
%A Park, S.
%A Kang, J.
%A Seo, J.
%A Anders, J.
%A Flynn, M.
%B 2007 IEEE Symposium on VLSI Circuits
%D 2007
%K ADC Pipeline
%P 194-195
%R 10.1109/VLSIC.2007.4342711
%T A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC
%U https://ieeexplore.ieee.org/document/4342711/
%X A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves a measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 1.62V supply. The measured dynamic range figure of merit is 174dB.
@inproceedings{4342711,
abstract = {A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18μm CMOS. The 22MS/s ADC achieves a measured DR of 80dB and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 1.62V supply. The measured dynamic range figure of merit is 174dB.},
added-at = {2020-10-11T10:03:42.000+0200},
author = {{Lee}, J. and {Park}, S. and {Kang}, J. and {Seo}, J. and {Anders}, J. and {Flynn}, M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/281f762cf5026d780a6e9056edd0a1f6e/jens.anders},
booktitle = {2007 IEEE Symposium on VLSI Circuits},
doi = {10.1109/VLSIC.2007.4342711},
interhash = {392371449194ee4ef3c8addd4ac1a6c8},
intrahash = {81f762cf5026d780a6e9056edd0a1f6e},
issn = {2158-5636},
keywords = {ADC Pipeline},
month = {June},
pages = {194-195},
timestamp = {2020-10-12T13:50:53.000+0200},
title = {A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC},
url = {https://ieeexplore.ieee.org/document/4342711/},
year = 2007
}