%0 Conference Paper %1 mohamed2022currentmode %A Mohamed, A. %A Baumgärtner, L. %A Zhao, J. %A Djekic, D. %A Anders, J. %B 2022 IEEE International Symposium on Circuits and Systems (ISCAS) %D 2022 %K iis myown %P 1-5 %T A current-mode Σ∆ modulator with FIR feedback and DC servo loop for an improved dynamic range %X In this paper, we present a continuous-time current-mode Σ∆ modulator (CT C-SDM) with finite impulse response (FIR) feedback to increase clock jitter robustness while preserving the anti-aliasing filtering (AAF) property of a CT modulator. The modulator also features a newly proposed DC servo loop (DSL) that extends the modulator’s dynamic range in applications with a large DC bias current. This improvement breaks the intrinsic tradeoff between dynamic range and quantization noise floor of C-SDM for applications which require the digitization of AC currents in the presence of strong DC bias currents. Moreover, a resistive-steering DAC is proposed that allows for larger sampling frequencies than conventional resistive DACs while, at the same time, achieving lower noise floors compared to current-steering DACs. The proposed modulator architecture has been manufactured in 180 nm CMOS, and consumes 64 mW from a 3.3 V supply. The chip’s measured peak SNR and SNDR are 77 dB and 76.8 dB, respectively. The modulator can accommodate AC signal currents up to 137 µApp and features an integrated noise of 6.9 nArms over a 200 kHz bandwidth, corresponding to a noise floor of 15 pA/√Hz. An off-chip implementation of the proposed DSL verifies its positive effect on the modulator’s dynamic range (DR) without deteriorating the modulator’s noise performance and/or stability properties.

@inproceedings{mohamed2022currentmode, abstract = {In this paper, we present a continuous-time current-mode Σ∆ modulator (CT C-SDM) with finite impulse response (FIR) feedback to increase clock jitter robustness while preserving the anti-aliasing filtering (AAF) property of a CT modulator. The modulator also features a newly proposed DC servo loop (DSL) that extends the modulator’s dynamic range in applications with a large DC bias current. This improvement breaks the intrinsic tradeoff between dynamic range and quantization noise floor of C-SDM for applications which require the digitization of AC currents in the presence of strong DC bias currents. Moreover, a resistive-steering DAC is proposed that allows for larger sampling frequencies than conventional resistive DACs while, at the same time, achieving lower noise floors compared to current-steering DACs. The proposed modulator architecture has been manufactured in 180 nm CMOS, and consumes 64 mW from a 3.3 V supply. The chip’s measured peak SNR and SNDR are 77 dB and 76.8 dB, respectively. The modulator can accommodate AC signal currents up to 137 µApp and features an integrated noise of 6.9 nArms over a 200 kHz bandwidth, corresponding to a noise floor of 15 pA/√Hz. An off-chip implementation of the proposed DSL verifies its positive effect on the modulator’s dynamic range (DR) without deteriorating the modulator’s noise performance and/or stability properties.}, added-at = {2022-03-14T10:42:59.000+0100}, author = {{Mohamed}, A. and {Baumgärtner}, L. and {Zhao}, J. and {Djekic}, D. and {Anders}, J.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23ac60754daee8c2c620391bf40504acd/aymanmohamed}, booktitle = {2022 IEEE International Symposium on Circuits and Systems (ISCAS)}, interhash = {82f4e818cac64bc5e7b834ce3d233ae9}, intrahash = {3ac60754daee8c2c620391bf40504acd}, keywords = {iis myown}, pages = {1-5}, timestamp = {2022-03-14T09:47:34.000+0100}, title = {A current-mode Σ∆ modulator with FIR feedback and DC servo loop for an improved dynamic range}, year = 2022 }