A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.
%0 Journal Article
%1 5256979
%A Lee, J.
%A Kang, J.
%A Park, S.
%A Seo, J.
%A Anders, J.
%A Guilherme, J.
%A Flynn, M. P.
%D 2009
%J IEEE Journal of Solid-State Circuits
%K ADC Pipeline
%N 10
%P 2755-2765
%R 10.1109/JSSC.2009.2028052
%T A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC
%U https://ieeexplore.ieee.org/document/5256979/
%V 44
%X A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.
@article{5256979,
abstract = {A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.},
added-at = {2020-10-11T10:09:38.000+0200},
author = {{Lee}, J. and {Kang}, J. and {Park}, S. and {Seo}, J. and {Anders}, J. and {Guilherme}, J. and {Flynn}, M. P.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/21bab7658d2a82680f3d21a1239f16f62/jens.anders},
doi = {10.1109/JSSC.2009.2028052},
interhash = {0a82ec6c4c6bc5442ec9d62e8ec275c3},
intrahash = {1bab7658d2a82680f3d21a1239f16f62},
issn = {1558-173X},
journal = {IEEE Journal of Solid-State Circuits},
keywords = {ADC Pipeline},
month = oct,
number = 10,
pages = {2755-2765},
timestamp = {2020-10-12T13:49:09.000+0200},
title = {A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC},
url = {https://ieeexplore.ieee.org/document/5256979/},
volume = 44,
year = 2009
}