%0 Conference Paper %1 conf/fpl/CuvelandRAL08 %A de Cuveland, Jan %A Rettig, Felix %A Angelov, Venelin %A Lindenstruth, Volker %B FPL %D 2008 %I IEEE %K dblp %P 293-298 %T An FPGA-based high-speed, low-latency trigger processor for high-energy physics. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2008.html#CuvelandRAL08 %@ 978-1-4244-1961-6

@inproceedings{conf/fpl/CuvelandRAL08, added-at = {2009-02-25T00:00:00.000+0100}, author = {de Cuveland, Jan and Rettig, Felix and Angelov, Venelin and Lindenstruth, Volker}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2937227e99108c2f12878c63bd47a91cd/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2008}, ee = {http://dx.doi.org/10.1109/FPL.2008.4629947}, interhash = {fb777a538b232c141a02e949c7d727b8}, intrahash = {937227e99108c2f12878c63bd47a91cd}, isbn = {978-1-4244-1961-6}, keywords = {dblp}, pages = {293-298}, publisher = {IEEE}, timestamp = {2016-04-27T09:33:01.000+0200}, title = {An FPGA-based high-speed, low-latency trigger processor for high-energy physics.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2008.html#CuvelandRAL08}, year = 2008 }