%0 Conference Paper %1 conf/fpga/AndradeGLMPRTWY12 %A Andrade, Hugo A. %A Ghosal, Arkadeb %A Limaye, Rhishikesh %A Malik, Sadia %A Petersen, Newton %A Ravindran, Kaushik %A Tran, Trung N. %A Wang, Guoqiang %A Yang, Guang %B FPGA %D 2012 %E Compton, Katherine %E Hutchings, Brad L. %I ACM %K dblp %P 271 %T Early timing estimation for system-level design using FPGAs (abstract only). %U http://dblp.uni-trier.de/db/conf/fpga/fpga2012.html#AndradeGLMPRTWY12 %@ 978-1-4503-1155-7

@inproceedings{conf/fpga/AndradeGLMPRTWY12, added-at = {2018-11-06T00:00:00.000+0100}, author = {Andrade, Hugo A. and Ghosal, Arkadeb and Limaye, Rhishikesh and Malik, Sadia and Petersen, Newton and Ravindran, Kaushik and Tran, Trung N. and Wang, Guoqiang and Yang, Guang}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/20e963bed2a6999e49c70b8a96ba5af94/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2012}, editor = {Compton, Katherine and Hutchings, Brad L.}, ee = {https://doi.org/10.1145/2145694.2145761}, interhash = {1f6292e9dd5d2df138ce0a3ad824b039}, intrahash = {0e963bed2a6999e49c70b8a96ba5af94}, isbn = {978-1-4503-1155-7}, keywords = {dblp}, pages = 271, publisher = {ACM}, timestamp = {2019-09-27T13:25:36.000+0200}, title = {Early timing estimation for system-level design using FPGAs (abstract only).}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2012.html#AndradeGLMPRTWY12}, year = 2012 }