This paper introduces the system architecture, implementation and measured characterization of the FPGA-based adaptive onboard payload computer used for an in-orbit verification of an E-band high bandwidth communication system. The mission goal is to evaluate the atmospheric effects on a multiGigabit data-downlink, in the frequency range of 71-76 GHz with a data rate of minimum 10 Gbit/s, from a 6U CubeSat in low earth orbit to a ground station. The miniaturized onboard payload computer in conjunction with a fast digital-to-analog converter shall serve as an arbitrary waveform generator and as image processing unit.
%0 Journal Article
%1 Manoliu_SHARC2021
%A Manoliu, Laura
%A Schoch, Benjamin
%A Koller, Markus
%A Wieczorek, Jens
%A Klinkner, Sabine
%A Kallfass, Ingmar
%B 2021 IEEE Space Hardware and Radio Conference (SHaRC)
%D 2021
%K imported
%P 21-24
%R 10.1109/SHaRC51853.2021.9375827
%T High-speed FPGA-Based Payload Computer for an In-Orbit Verification of a 71--76 GHz Satellite Downlink
%X This paper introduces the system architecture, implementation and measured characterization of the FPGA-based adaptive onboard payload computer used for an in-orbit verification of an E-band high bandwidth communication system. The mission goal is to evaluate the atmospheric effects on a multiGigabit data-downlink, in the frequency range of 71-76 GHz with a data rate of minimum 10 Gbit/s, from a 6U CubeSat in low earth orbit to a ground station. The miniaturized onboard payload computer in conjunction with a fast digital-to-analog converter shall serve as an arbitrary waveform generator and as image processing unit.
@article{Manoliu_SHARC2021,
abstract = {This paper introduces the system architecture, implementation and measured characterization of the FPGA-based adaptive onboard payload computer used for an in-orbit verification of an E-band high bandwidth communication system. The mission goal is to evaluate the atmospheric effects on a multiGigabit data-downlink, in the frequency range of 71-76 GHz with a data rate of minimum 10 Gbit/s, from a 6U CubeSat in low earth orbit to a ground station. The miniaturized onboard payload computer in conjunction with a fast digital-to-analog converter shall serve as an arbitrary waveform generator and as image processing unit.},
added-at = {2022-11-04T11:48:46.000+0100},
author = {Manoliu, Laura and Schoch, Benjamin and Koller, Markus and Wieczorek, Jens and Klinkner, Sabine and Kallfass, Ingmar},
bdsk-url-1 = {https://doi.org/10.1109/SHaRC51853.2021.9375827},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2f8fdb0f19b2a70f2bfa6183f9b79eec0/ingmarkallfass},
booktitle = {2021 IEEE Space Hardware and Radio Conference (SHaRC)},
date-added = {2021-12-17 13:26:37 +0100},
date-modified = {2021-12-17 13:27:39 +0100},
doi = {10.1109/SHaRC51853.2021.9375827},
interhash = {f40dd76bd1a5bf20671bc42b236e80d2},
intrahash = {f8fdb0f19b2a70f2bfa6183f9b79eec0},
keywords = {imported},
month = Jan,
pages = {21-24},
timestamp = {2022-11-04T10:48:46.000+0100},
title = {High-speed FPGA-Based Payload Computer for an In-Orbit Verification of a 71--76 GHz Satellite Downlink},
year = 2021
}
