%0 Conference Paper %1 conf/vlsid/RaviGRD98 %A Ravi, Srivaths %A Ghosh, Indradeep %A Roy, Rabindra K. %A Dey, Sujit %B VLSI Design %D 1998 %I IEEE Computer Society %K dblp %P 193-198 %T Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1998.html#RaviGRD98 %@ 0-8186-8224-8

@inproceedings{conf/vlsid/RaviGRD98, added-at = {2016-05-30T00:00:00.000+0200}, author = {Ravi, Srivaths and Ghosh, Indradeep and Roy, Rabindra K. and Dey, Sujit}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b13ed350073607155bf07bfe7c563401/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1998}, ee = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646601}, interhash = {1ebe7fdd37698c9037f9bf0bd76bc771}, intrahash = {b13ed350073607155bf07bfe7c563401}, isbn = {0-8186-8224-8}, keywords = {dblp}, pages = {193-198}, publisher = {IEEE Computer Society}, timestamp = {2016-05-31T09:49:50.000+0200}, title = {Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1998.html#RaviGRD98}, year = 1998 }