%0 Conference Paper %1 conf/vlsid/AhmedNRNFR93 %A Ahmed, Suhail %A Nagesh, T. V. %A Rao, Ramoji %A Naveen, B. %A Fangaria, P. K. %A Raghunathan, K. S. %B VLSI Design %D 1993 %I IEEE Computer Society %K dblp %P 73-79 %T FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1993.html#AhmedNRNFR93 %@ 0-8186-3180-5

@inproceedings{conf/vlsid/AhmedNRNFR93, added-at = {2019-02-15T00:00:00.000+0100}, author = {Ahmed, Suhail and Nagesh, T. V. and Rao, Ramoji and Naveen, B. and Fangaria, P. K. and Raghunathan, K. S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/28b1c665bdcb589d56d9e776dca780852/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1993}, ee = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1993.669642}, interhash = {e92516759410f03be833e44a3d43b1e8}, intrahash = {8b1c665bdcb589d56d9e776dca780852}, isbn = {0-8186-3180-5}, keywords = {dblp}, pages = {73-79}, publisher = {IEEE Computer Society}, timestamp = {2019-09-27T18:12:18.000+0200}, title = {FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1993.html#AhmedNRNFR93}, year = 1993 }