%0 Conference Paper %1 conf/vlsid/CzutroRPB14 %A Czutro, Alexander %A Reddy, Sudhakar M. %A Polian, Ilia %A Becker, Bernd %B VLSI Design %D 2014 %I IEEE Computer Society %K dblp %P 56-61 %T SAT-Based Test Pattern Generation with Improved Dynamic Compaction. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2014.html#CzutroRPB14 %@ 978-1-4799-2513-1

@inproceedings{conf/vlsid/CzutroRPB14, added-at = {2015-04-21T00:00:00.000+0200}, author = {Czutro, Alexander and Reddy, Sudhakar M. and Polian, Ilia and Becker, Bernd}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2fb80b21899661046f21758d5cd4ed6b5/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2014}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2014.17}, interhash = {e4f6b353ba2813add5112c9791273f66}, intrahash = {fb80b21899661046f21758d5cd4ed6b5}, isbn = {978-1-4799-2513-1}, keywords = {dblp}, pages = {56-61}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T11:08:46.000+0100}, title = {SAT-Based Test Pattern Generation with Improved Dynamic Compaction.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2014.html#CzutroRPB14}, year = 2014 }