%0 Journal Article %1 journals/vlsi/Hu0D11 %A Hu, Shiyan %A Li, Zhuo %A Deng, Yangdong %D 2011 %J VLSI Design %K dblp %P 398390:1-398390:2 %T CAD for Gigascale SoC Design and Verification Solutions. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi2011.html#Hu0D11 %V 2011

@article{journals/vlsi/Hu0D11, added-at = {2018-11-24T00:00:00.000+0100}, author = {Hu, Shiyan and Li, Zhuo and Deng, Yangdong}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/28f947475f67ecd400823d8b290a984da/dblp}, ee = {https://www.wikidata.org/entity/Q58694517}, interhash = {dd3b04b2a7df969abe942bf989637301}, intrahash = {8f947475f67ecd400823d8b290a984da}, journal = {VLSI Design}, keywords = {dblp}, pages = {398390:1-398390:2}, timestamp = {2019-09-27T06:27:47.000+0200}, title = {CAD for Gigascale SoC Design and Verification Solutions.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi2011.html#Hu0D11}, volume = 2011, year = 2011 }