%0 Journal Article %1 journals/tcad/HuSMH08 %A Hu, Yu %A Shih, Victor %A Majumdar, Rupak %A He, Lei %D 2008 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 10 %P 1751-1760 %T Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. %U http://dblp.uni-trier.de/db/journals/tcad/tcad27.html#HuSMH08 %V 27

@article{journals/tcad/HuSMH08, added-at = {2009-03-20T00:00:00.000+0100}, author = {Hu, Yu and Shih, Victor and Majumdar, Rupak and He, Lei}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/26252f5459426e4d0c347cdf356ffa886/dblp}, ee = {http://dx.doi.org/10.1109/TCAD.2008.2003272}, interhash = {d9050ad103d99caf84e9c7a3644be23c}, intrahash = {6252f5459426e4d0c347cdf356ffa886}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 10, pages = {1751-1760}, timestamp = {2016-02-02T10:07:38.000+0100}, title = {Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad27.html#HuSMH08}, volume = 27, year = 2008 }