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%0 Conference Paper
%1 conf/icadl/PrasadDS03a
%A Prasad, P. W. Chandana
%A Dominic, M. Maria
%A Singh, Ashutosh Kumar
%B ICADL
%D 2003
%E Sembok, Tengku M. T.
%E Zaman, Halimah Badioze
%E Chen, Hsinchun
%E Urs, Shalini R.
%E Myaeng, Sung-Hyon
%I Springer
%K dblp
%P 689
%T Variable Order Verification Use of Logic Representation.
%U http://dblp.uni-trier.de/db/conf/icadl/icadl2003.html#PrasadDS03a
%V 2911
%@ 3-540-20608-6
@inproceedings{conf/icadl/PrasadDS03a,
added-at = {2017-05-26T00:00:00.000+0200},
author = {Prasad, P. W. Chandana and Dominic, M. Maria and Singh, Ashutosh Kumar},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d0389100064e75a005c63a9f456fcc45/dblp},
booktitle = {ICADL},
crossref = {conf/icadl/2003},
editor = {Sembok, Tengku M. T. and Zaman, Halimah Badioze and Chen, Hsinchun and Urs, Shalini R. and Myaeng, Sung-Hyon},
ee = {https://doi.org/10.1007/978-3-540-24594-0_78},
interhash = {ce2d7b2b8188ca96a2f39cd78b4e8345},
intrahash = {d0389100064e75a005c63a9f456fcc45},
isbn = {3-540-20608-6},
keywords = {dblp},
pages = 689,
publisher = {Springer},
series = {Lecture Notes in Computer Science},
timestamp = {2019-09-27T13:37:40.000+0200},
title = {Variable Order Verification Use of Logic Representation.},
url = {http://dblp.uni-trier.de/db/conf/icadl/icadl2003.html#PrasadDS03a},
volume = 2911,
year = 2003
}
