%0 Journal Article %1 journals/tcad/JhaveriRLPSH10 %A Jhaveri, Tejas %A Rovner, Vyacheslav %A Liebmann, Lars %A Pileggi, Larry T. %A Strojwas, Andrzej J. %A Hibbeler, Jason %D 2010 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 4 %P 509-527 %T Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. %U http://dblp.uni-trier.de/db/journals/tcad/tcad29.html#JhaveriRLPSH10 %V 29

@article{journals/tcad/JhaveriRLPSH10, added-at = {2011-01-12T00:00:00.000+0100}, author = {Jhaveri, Tejas and Rovner, Vyacheslav and Liebmann, Lars and Pileggi, Larry T. and Strojwas, Andrzej J. and Hibbeler, Jason}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/22f1148755fe2ec66cd827110c05b4f48/dblp}, ee = {http://dx.doi.org/10.1109/TCAD.2010.2042882}, interhash = {c652469461ef015a712ca2810d731078}, intrahash = {2f1148755fe2ec66cd827110c05b4f48}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 4, pages = {509-527}, timestamp = {2016-02-02T10:07:43.000+0100}, title = {Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad29.html#JhaveriRLPSH10}, volume = 29, year = 2010 }