%0 Journal Article %1 journals/tvlsi/AliAC19 %A Ali, Muhammad %A Ahmed, Mohammad A. %A Chrzanowska-Jeske, Malgorzata %D 2019 %J IEEE Trans. VLSI Syst. %K dblp %N 3 %P 573-586 %T Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#AliAC19 %V 27

@article{journals/tvlsi/AliAC19, added-at = {2019-04-12T00:00:00.000+0200}, author = {Ali, Muhammad and Ahmed, Mohammad A. and Chrzanowska-Jeske, Malgorzata}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c14e0dda3c93f4f3e0b8570d4751cb05/dblp}, ee = {https://doi.org/10.1109/TVLSI.2018.2880322}, interhash = {77c58e218911ee5849c58df42750a436}, intrahash = {c14e0dda3c93f4f3e0b8570d4751cb05}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 3, pages = {573-586}, timestamp = {2019-09-27T06:53:22.000+0200}, title = {Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#AliAC19}, volume = 27, year = 2019 }