%0 Conference Paper %1 conf/vlsic/NamHZC16 %A Nam, Jae-Won %A Hassanpourghadi, Mohsen %A Zhang, Aoyang %A Chen, Mike Shuo-Wei %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#NamHZC16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/NamHZC16, added-at = {2016-09-26T00:00:00.000+0200}, author = {Nam, Jae-Won and Hassanpourghadi, Mohsen and Zhang, Aoyang and Chen, Mike Shuo-Wei}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23f047ce697fb9391c1498311c22aa4a4/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {http://dx.doi.org/10.1109/VLSIC.2016.7573516}, interhash = {6a15629fb6a8177861070d1dc9feaf4b}, intrahash = {3f047ce697fb9391c1498311c22aa4a4}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2016-09-27T09:35:47.000+0200}, title = {A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#NamHZC16}, year = 2016 }