%0 Journal Article %1 journals/tvlsi/JiangXCM12 %A Jiang, Li %A Xu, Qiang %A Chakrabarty, Krishnendu %A Mak, T. M. %D 2012 %J IEEE Trans. VLSI Syst. %K dblp %N 9 %P 1621-1633 %T Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi20.html#JiangXCM12 %V 20

@article{journals/tvlsi/JiangXCM12, added-at = {2012-07-18T00:00:00.000+0200}, author = {Jiang, Li and Xu, Qiang and Chakrabarty, Krishnendu and Mak, T. M.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2f3f8caa65e5710252702d92af2f34aab/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2011.2160410}, interhash = {651d6821de7fc94f12b9a0ccfd5fad84}, intrahash = {f3f8caa65e5710252702d92af2f34aab}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 9, pages = {1621-1633}, timestamp = {2016-02-02T02:13:23.000+0100}, title = {Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi20.html#JiangXCM12}, volume = 20, year = 2012 }