%0 Conference Paper %1 hanel2018performance %A Hänel, L. A. %A Elogail, Y. %A Schwarz, Daniel %A Fischer, Inga A. %A Schulze, Jörg %B 2018 41st International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO) %D 2018 %I IEEE %K %P 0027-0031 %R 10.23919/MIPRO.2018.8400005 %T Performance of C6H8O7-treated and H- and Cl-passivated Ge-MOS-capacitances on Ge-virtual-substrate on Si(001) %X As Moore's law is approaching its physical limitations, transistor concepts besides the classical Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) have been invented. The Tunneling FET (TFET) is a promising candidate due to the theoretically predicted subthreshold swing below 60 mV/dec of this device concept. However, Si is not the substrate of choice for TFETs - the carrier mobility and the resulting on-currents are too low. Therefore, Germanium (Ge) is suggested as active material for p-channel TFET (p-TFET) as compound III/V-materials are suggested as n-TFET active material with a high-k material as Gate oxide. This development entails new issues in the manufacturing process. That is because the Ge/high-k-interface is not of natural high quality as the Si/SiO2-interface, causing the Gate-MOS-capacitance to be the critical part of the TFET. New cleaning and passivation methods for the Ge surface are necessary. Nevertheless, Si will remain the substrate material of choice, what requires co-integration of those materials on Si. As a first attempt, we show Ge-MOS-capacitors with Al2O3as Gate Oxide on Ge-Virtual-Substrate on Si(001) of good performance with hysteresis down to 0.6 V. We propose a combination of conventional and unconventional cleaning steps such as H2O2and C6H8O7(Citric Acid) followed by H- and Cl-passivation. The discussed data are corrected for series resistance and - when possible - for parasitic capacitances that can be used as indicators for cleaning and passivation efficiencies. %@ 978-953-233-095-3 and 978-953-233-097-7 and 978-1-5386-3777-7

@inproceedings{hanel2018performance, abstract = {As Moore's law is approaching its physical limitations, transistor concepts besides the classical Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) have been invented. The Tunneling FET (TFET) is a promising candidate due to the theoretically predicted subthreshold swing below 60 mV/dec of this device concept. However, Si is not the substrate of choice for TFETs - the carrier mobility and the resulting on-currents are too low. Therefore, Germanium (Ge) is suggested as active material for p-channel TFET (p-TFET) as compound III/V-materials are suggested as n-TFET active material with a high-k material as Gate oxide. This development entails new issues in the manufacturing process. That is because the Ge/high-k-interface is not of natural high quality as the Si/SiO2-interface, causing the Gate-MOS-capacitance to be the critical part of the TFET. New cleaning and passivation methods for the Ge surface are necessary. Nevertheless, Si will remain the substrate material of choice, what requires co-integration of those materials on Si. As a first attempt, we show Ge-MOS-capacitors with Al2O3as Gate Oxide on Ge-Virtual-Substrate on Si(001) of good performance with hysteresis down to 0.6 V. We propose a combination of conventional and unconventional cleaning steps such as H2O2and C6H8O7(Citric Acid) followed by H- and Cl-passivation. The discussed data are corrected for series resistance and - when possible - for parasitic capacitances that can be used as indicators for cleaning and passivation efficiencies.}, added-at = {2023-08-31T15:09:47.000+0200}, author = {Hänel, L. A. and Elogail, Y. and Schwarz, Daniel and Fischer, Inga A. and Schulze, Jörg}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2db2f737ccef7e12db248931f6cf2ca43/puma-wartung}, booktitle = {2018 41st International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO)}, doi = {10.23919/MIPRO.2018.8400005}, eventdate = {2018-05-21/2018-05-25}, eventtitle = {41st International Convention on Information and Communication Technology, Electronics and Microelectronics 2018 (MIPRO)}, interhash = {15c304cefe9f7f72a15351ae11424a4c}, intrahash = {db2f737ccef7e12db248931f6cf2ca43}, isbn = {{978-953-233-095-3} and {978-953-233-097-7} and {978-1-5386-3777-7}}, keywords = {}, language = {eng}, pages = {0027-0031}, publisher = {IEEE}, timestamp = {2023-08-31T13:09:47.000+0200}, title = {Performance of C6H8O7-treated and H- and Cl-passivated Ge-MOS-capacitances on Ge-virtual-substrate on Si(001)}, venue = {Opatija, Croatia}, year = 2018 }