%0 Journal Article %1 journals/tvlsi/YehM04 %A Yeh, Chao-Yang %A Marek-Sadowska, Malgorzata %D 2004 %J IEEE Trans. VLSI Syst. %K dblp %N 10 %P 1028-1037 %T Sequential delay budgeting with interconnect prediction. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#YehM04 %V 12

@article{journals/tvlsi/YehM04, added-at = {2016-03-15T00:00:00.000+0100}, author = {Yeh, Chao-Yang and Marek-Sadowska, Malgorzata}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2128fb9b59706f5b03bfe306f06bac63a/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2004.827563}, interhash = {55c94636a8a9872f9c90ec58fe84f0ea}, intrahash = {128fb9b59706f5b03bfe306f06bac63a}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 10, pages = {1028-1037}, timestamp = {2016-03-16T10:31:54.000+0100}, title = {Sequential delay budgeting with interconnect prediction.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#YehM04}, volume = 12, year = 2004 }