%0 Conference Paper %1 conf/fpl/AhmedZTB17 %A Ahmed, Ibrahim %A Zhao, Shuze %A Trescases, Olivier %A Betz, Vaughn %B FPL %D 2017 %E Santambrogio, Marco D. %E Göhringer, Diana %E Stroobandt, Dirk %E Mentens, Nele %E Nurmi, Jari %I IEEE %K dblp %P 1-8 %T Find the real speed limit: FPGA CAD for chip-specific application delay measurement. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2017.html#AhmedZTB17 %@ 978-9-0903-0428-1

@inproceedings{conf/fpl/AhmedZTB17, added-at = {2019-02-18T00:00:00.000+0100}, author = {Ahmed, Ibrahim and Zhao, Shuze and Trescases, Olivier and Betz, Vaughn}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2055f5fa994997bf338522033bb42aff2/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2017}, editor = {Santambrogio, Marco D. and Göhringer, Diana and Stroobandt, Dirk and Mentens, Nele and Nurmi, Jari}, ee = {https://doi.org/10.23919/FPL.2017.8056819}, interhash = {427d8374862c072f4028b5058c61887f}, intrahash = {055f5fa994997bf338522033bb42aff2}, isbn = {978-9-0903-0428-1}, keywords = {dblp}, pages = {1-8}, publisher = {IEEE}, timestamp = {2019-09-27T19:42:05.000+0200}, title = {Find the real speed limit: FPGA CAD for chip-specific application delay measurement.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2017.html#AhmedZTB17}, year = 2017 }