%0 Conference Paper %1 conf/fpl/MeiVVML03 %A Mei, Bingfeng %A Vernalde, Serge %A Verkest, Diederik %A Man, Hugo De %A Lauwereins, Rudy %B FPL %D 2003 %E Cheung, Peter Y. K. %E Constantinides, George A. %E de Sousa, José T. %I Springer %K dblp %P 61-70 %T ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2003.html#MeiVVML03 %V 2778 %@ 3-540-40822-3

@inproceedings{conf/fpl/MeiVVML03, added-at = {2017-05-21T00:00:00.000+0200}, author = {Mei, Bingfeng and Vernalde, Serge and Verkest, Diederik and Man, Hugo De and Lauwereins, Rudy}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2cd6cb939793d2e0558f136c2b33bc21b/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2003}, editor = {Cheung, Peter Y. K. and Constantinides, George A. and de Sousa, José T.}, ee = {https://doi.org/10.1007/978-3-540-45234-8_7}, interhash = {3ad11a9e320cbdf778dc4c2bd12453fe}, intrahash = {cd6cb939793d2e0558f136c2b33bc21b}, isbn = {3-540-40822-3}, keywords = {dblp}, pages = {61-70}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2019-09-27T14:36:34.000+0200}, title = {ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2003.html#MeiVVML03}, volume = 2778, year = 2003 }