%0 Conference Paper %1 conf/vlsid/NarasimhanDES05 %A Narasimhan, Ashok %A Divekar, Shantanu %A Elakkumanan, Praveen %A Sridhar, Ramalingam %B VLSI Design %D 2005 %I IEEE Computer Society %K dblp %P 130-133 %T A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#NarasimhanDES05 %@ 0-7695-2264-5

@inproceedings{conf/vlsid/NarasimhanDES05, added-at = {2017-05-23T00:00:00.000+0200}, author = {Narasimhan, Ashok and Divekar, Shantanu and Elakkumanan, Praveen and Sridhar, Ramalingam}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b9ca405bf0443fbfb17e103342756580/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2005}, ee = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.18}, interhash = {363b8b404072dd0612fe019ecf240c33}, intrahash = {b9ca405bf0443fbfb17e103342756580}, isbn = {0-7695-2264-5}, keywords = {dblp}, pages = {130-133}, publisher = {IEEE Computer Society}, timestamp = {2019-09-27T18:12:10.000+0200}, title = {A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#NarasimhanDES05}, year = 2005 }