This paper introduces an architecture and design for high-resolution high-linearity Nyquist rate successive approximation register (SAR) analog-to-digital converters (ADCs) using a hybrid capacitive and incremental ΣA digital-to-analog converter (DAC). The proposed architecture benefits from an intrinsically linear 1.5-bit ΣA DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC (CDAC). The achieved linearity relies neither on a highly matched CDAC nor on any dynamic linearization techniques but on a single calibration of the coarse CDAC using the available ΣA DAC at startup. Therefore, the CDAC can be sized solely upon noise requirements. The SAR ADC employs two parallel dynamic comparators for improved power efficiency. A prototype was fabricated in a 40-nm CMOS, with power supplies of 1.1 and 2.5 V. It occupies an active area of only 0.074 mm2. The prototype achieves a measured peak spurious free dynamic range (SFDR) of 107 dB and peak signal to noise and distortion ratio (SNDR) of 84.8 dB dB at 80kS/s Nyquist rate operation with 5.3-kHz input. The measured performance at the Nyquist frequency, limited by signal source quality, is SFDR = 99.5 dB and SNDR = 83.5 dB. The core power consumption is 110 μW. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5-kHz bandwidth.
%0 Journal Article
%1 8207772
%A AlMarashli, A.
%A Anders, J.
%A Becker, J.
%A Ortmanns, M.
%D 2018
%J IEEE Journal of Solid-State Circuits
%K ADC SAR
%N 5
%P 1493-1507
%R 10.1109/JSSC.2017.2776299
%T A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s
%U https://ieeexplore.ieee.org/document/8207772/
%V 53
%X This paper introduces an architecture and design for high-resolution high-linearity Nyquist rate successive approximation register (SAR) analog-to-digital converters (ADCs) using a hybrid capacitive and incremental ΣA digital-to-analog converter (DAC). The proposed architecture benefits from an intrinsically linear 1.5-bit ΣA DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC (CDAC). The achieved linearity relies neither on a highly matched CDAC nor on any dynamic linearization techniques but on a single calibration of the coarse CDAC using the available ΣA DAC at startup. Therefore, the CDAC can be sized solely upon noise requirements. The SAR ADC employs two parallel dynamic comparators for improved power efficiency. A prototype was fabricated in a 40-nm CMOS, with power supplies of 1.1 and 2.5 V. It occupies an active area of only 0.074 mm2. The prototype achieves a measured peak spurious free dynamic range (SFDR) of 107 dB and peak signal to noise and distortion ratio (SNDR) of 84.8 dB dB at 80kS/s Nyquist rate operation with 5.3-kHz input. The measured performance at the Nyquist frequency, limited by signal source quality, is SFDR = 99.5 dB and SNDR = 83.5 dB. The core power consumption is 110 μW. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5-kHz bandwidth.
@article{8207772,
abstract = {This paper introduces an architecture and design for high-resolution high-linearity Nyquist rate successive approximation register (SAR) analog-to-digital converters (ADCs) using a hybrid capacitive and incremental ΣA digital-to-analog converter (DAC). The proposed architecture benefits from an intrinsically linear 1.5-bit ΣA DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC (CDAC). The achieved linearity relies neither on a highly matched CDAC nor on any dynamic linearization techniques but on a single calibration of the coarse CDAC using the available ΣA DAC at startup. Therefore, the CDAC can be sized solely upon noise requirements. The SAR ADC employs two parallel dynamic comparators for improved power efficiency. A prototype was fabricated in a 40-nm CMOS, with power supplies of 1.1 and 2.5 V. It occupies an active area of only 0.074 mm2. The prototype achieves a measured peak spurious free dynamic range (SFDR) of 107 dB and peak signal to noise and distortion ratio (SNDR) of 84.8 dB dB at 80kS/s Nyquist rate operation with 5.3-kHz input. The measured performance at the Nyquist frequency, limited by signal source quality, is SFDR = 99.5 dB and SNDR = 83.5 dB. The core power consumption is 110 μW. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5-kHz bandwidth.},
added-at = {2020-10-11T10:15:52.000+0200},
author = {{AlMarashli}, A. and {Anders}, J. and {Becker}, J. and {Ortmanns}, M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b00ab97756ebf55598d2226853e4e225/jens.anders},
doi = {10.1109/JSSC.2017.2776299},
interhash = {2a4f71cd2b58de3698975a5c06605041},
intrahash = {b00ab97756ebf55598d2226853e4e225},
issn = {1558-173X},
journal = {IEEE Journal of Solid-State Circuits},
keywords = {ADC SAR},
month = may,
number = 5,
pages = {1493-1507},
timestamp = {2020-10-12T13:46:17.000+0200},
title = {A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s},
url = {https://ieeexplore.ieee.org/document/8207772/},
volume = 53,
year = 2018
}
