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A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR=107 dB at 80 kS/s

, , , and . Ieee Journal of Solid-State Circuits, 53 (5): 1493-1507 (2018)
DOI: 10.1109/Jssc.2017.2776299

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A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental Sigma Delta DAC, , , and . 2017 Symposium on Vlsi Circuits, (2017)Design of a High Linearity Gm Stage for a High Speed Current Mode SAR ADC, , , , and . 2014 21st Ieee International Conference on Electronics, Circuits and Systems (Icecs), (2014)Employing Incremental Sigma Delta DACs for High Resolution SAR ADC, , and . 2014 21st Ieee International Conference on Electronics, Circuits and Systems (Icecs), (2014)A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental ΣΔ DAC, , , and . 2017 Symposium on VLSI Circuits, page C240-C241. (June 2017)Design study on a SAR ADC using an incremental ΣΔ-DAC, , and . 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), page 172-175. (June 2015)A Hybrid Comparator for High Resolution SAR ADC, , and . 2016 Ieee International Symposium on Circuits and Systems (Iscas), (2016)A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR=107 dB at 80 kS/s, , , and . Ieee Journal of Solid-State Circuits, 53 (5): 1493-1507 (2018)Design study on a SAR ADC using an incremental Sigma Delta-DAC, , and . 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (Prime), (2015)