%0 Conference Paper %1 conf/vlsi/NocuaVB0C16 %A Nocua, Alejandro %A Virazel, Arnaud %A Bosio, Alberto %A Girard, Patrick %A Chevalier, Cyril %B VLSI-SoC %D 2016 %I IEEE %K dblp %P 1-6 %T A Hybrid Power Estimation Technique to improve IP power models quality. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2016.html#NocuaVB0C16 %@ 978-1-5090-3561-8

@inproceedings{conf/vlsi/NocuaVB0C16, added-at = {2016-12-18T00:00:00.000+0100}, author = {Nocua, Alejandro and Virazel, Arnaud and Bosio, Alberto and Girard, Patrick and Chevalier, Cyril}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2cd9bf3598e1f3c2bf7b7078411603f12/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2016soc}, ee = {http://dx.doi.org/10.1109/VLSI-SoC.2016.7753582}, interhash = {222489299a808b66db75620ecb9b991f}, intrahash = {cd9bf3598e1f3c2bf7b7078411603f12}, isbn = {978-1-5090-3561-8}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2016-12-20T10:35:24.000+0100}, title = {A Hybrid Power Estimation Technique to improve IP power models quality.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2016.html#NocuaVB0C16}, year = 2016 }