%0 Thesis %1 phd/hal/Bres02 %A Bres, Yannis %D 2002 %K dblp %T Exploration implicite et explicite de l'espace d''etats atteignables de circuits logiques Esterel.

@phdthesis{phd/hal/Bres02, added-at = {2016-07-18T00:00:00.000+0200}, author = {Bres, Yannis}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d4b880456ae3c4a77a89ab2b44405864/dblp}, ee = {https://tel.archives-ouvertes.fr/tel-00003600}, interhash = {1c7069741eaaa1fc90904984ce24a3ac}, intrahash = {d4b880456ae3c4a77a89ab2b44405864}, keywords = {dblp}, school = {University of Nice Sophia Antipolis, France}, timestamp = {2016-07-19T09:32:26.000+0200}, title = {Exploration implicite et explicite de l'espace d''etats atteignables de circuits logiques Esterel.}, year = 2002 }