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%0 Conference Paper
%1 conf/mse/BeckerBTMB03
%A Becker, Jens E.
%A Bieser, Carsten
%A Thomas, Alexander
%A Müller-Glaser, Klaus D.
%A Becker, Jürgen
%B MSE
%D 2003
%I IEEE Computer Society
%K dblp
%P 134-135
%T Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core.
%U http://dblp.uni-trier.de/db/conf/mse/mse2003.html#BeckerBTMB03
%@ 0-7695-1973-3
@inproceedings{conf/mse/BeckerBTMB03,
added-at = {2019-07-19T00:00:00.000+0200},
author = {Becker, Jens E. and Bieser, Carsten and Thomas, Alexander and Müller-Glaser, Klaus D. and Becker, Jürgen},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/21cb0c59946b92bae32d2d052b4586cf5/dblp},
booktitle = {MSE},
crossref = {conf/mse/2003},
ee = {http://doi.ieeecomputersociety.org/10.1109/MSE.2003.1205288},
interhash = {1979dce902d79ce19200be0a88cb7489},
intrahash = {1cb0c59946b92bae32d2d052b4586cf5},
isbn = {0-7695-1973-3},
keywords = {dblp},
pages = {134-135},
publisher = {IEEE Computer Society},
timestamp = {2019-09-27T21:07:54.000+0200},
title = {Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core.},
url = {http://dblp.uni-trier.de/db/conf/mse/mse2003.html#BeckerBTMB03},
year = 2003
}
