Publications

S. Fahmy, M. Dietl, P. Sareen, M. Ortmanns, und J. Anders. A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 mu m CMOS achieving 700 fs rms phase jitter. 2015 Nordic Circuits and Systems Conference (Norcas) - Norchip & International Symposium on System-on-Chip (Soc), 2015. [PUMA: PLL] URL

J. Anders, S. Bader, M. Dietl, P. Sareen, G. Rombach, S. Tambouris, und M. Ortmanns. A-245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS. 2017 Ieee Asian Solid-State Circuits Conference (a-Sscc), 325-328, 2017. [PUMA: PLL] URL