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2A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 mu m CMOS achieving 700 fs rms phase jitter
S. Fahmy, M. Dietl, P. Sareen, M. Ortmanns, and J. Anders. 2015 Nordic Circuits and Systems Conference (Norcas) - Norchip & International Symposium on System-on-Chip (Soc), (2015)
6 years ago by @jens.anders
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PLL
PLL
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3A-245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS
J. Anders, S. Bader, M. Dietl, P. Sareen, G. Rombach, S. Tambouris, and M. Ortmanns. 2017 Ieee Asian Solid-State Circuits Conference (a-Sscc), (2017)
6 years ago by @jens.anders
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PLL
PLL
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