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Power Consumption of Fault Tolerant Busses., , , , and . IEEE Trans. VLSI Syst., 16 (5): 542-553 (2008)Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?., , and . IEEE Trans. Computers, 56 (3): 415-428 (2007)Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems., , , , and . DFT, page 233-240. IEEE Computer Society, (1998)Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks., , and . DFT, page 174-182. IEEE Computer Society, (1998)Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block., , , and . DFT, page 271-278. IEEE Computer Society, (1993)Multiple Transient Faults in Logic: An Issue for Next Generation ICs., , , and . DFT, page 352-360. IEEE Computer Society, (2005)Compact and Highly Testable Error Indicator for Self-Checking Circuits., , and . DFT, page 204-212. IEEE Computer Society, (1996)Low-level error recovery mechanism for self-checking sequential circuits., and . DFT, page 234-242. IEEE Computer Society, (1997)Testing Resistive Opens and Bridging Faults Through Pulse Propagation., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (6): 915-925 (2009)Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates., , , and . J. Electronic Testing, 25 (1): 39-54 (2009)