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FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).

D. Dai, A. Vaidya, R. Saharoy, S. Park, D. Park, H. Thantry, R. Plate, E. Maas, A. Kumar, and M. Azimi. FPGA, page 293. ACM, (2010)

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Sumee Park

Soo Yong Park University of Stuttgart

Other publications of authors with the same name

On the Effects of Process Variation in Network-on-Chip Architectures.C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das, and M. Irwin. IEEE Trans. Dependable Sec. Comput., 7 (3): 240-254 (2010)MIRA: A Multi-layered On-Chip Interconnect Router Architecture.D. Park, S. Eachempati, R. Das, A. Mishra, Y. Xie, N. Vijaykrishnan, and C. Das. ISCA, page 251-261. IEEE Computer Society, (2008)ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.C. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M. Yousif, and C. Das. MICRO, page 333-346. IEEE Computer Society, (2006)MoDe-X: Microarchitecture of a Layout-Aware Modular Decoupled Crossbar for On-Chip Interconnects.D. Park, A. Vaidya, A. Kumar, and M. Azimi. IEEE Trans. Computers, 63 (3): 622-636 (2014)Performance and power optimization through data compression in Network-on-Chip architectures.R. Das, A. Mishra, C. Nicopoulos, D. Park, V. Narayanan, R. Iyer, M. Yousif, and C. Das. HPCA, page 215-225. IEEE Computer Society, (2008)A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.T. Richardson, C. Nicopoulos, D. Park, N. Vijaykrishnan, Y. Xie, C. Das, and V. Degalahal. VLSI Design, page 657-664. IEEE Computer Society, (2006)A novel dimensionally-decomposed router for on-chip communication in 3D architectures.J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, M. Yousif, and C. Das. ISCA, page 138-149. ACM, (2007)A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.J. Kim, C. Nicopoulos, D. Park, V. Narayanan, M. Yousif, and C. Das. ISCA, page 4-15. IEEE Computer Society, (2006)A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects.D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, and C. Das. Nano-Net, page 1-6. IEEE, (2006)Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects.D. Park, R. Das, C. Nicopoulos, J. Kim, N. Vijaykrishnan, R. Iyer, and C. Das. Hot Interconnects, page 15-20. IEEE Computer Society, (2007)

PUMA

Disambiguation of "Park, Dongkook"

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FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).

Please choose a person to relate this publication to

Sumee Park

Soo Yong Park University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Park, Dongkook"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).

Please choose a person to relate this publication to

Sumee Park

Soo Yong Park University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
DIN 1505
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FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).