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Reconfigurable architectures and processors for real-time video motion estimation.

, , , and . J. Real-Time Image Processing, 2 (4): 191-205 (2007)

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Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding., , and . SoCC, page 91-92. IEEE, (2005)Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units., , , , and . DSD, page 181-188. IEEE Computer Society, (2008)Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems., , and . DASIP, page 242-249. IEEE, (2010)A flexible architecture for the computation of direct and inverse transforms in H.264/AVC video codecs., , , and . IEEE Trans. Consumer Electronics, 57 (2): 936-944 (2011)High performance multi-standard architecture for DCT computation in H.264/AVC High Profile and HEVC codecs., , and . DASIP, page 14-21. IEEE, (2013)Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs., , and . EURASIP J. Adv. Sig. Proc., (2014)High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC., , , and . DSD, page 632-639. IEEE Computer Society, (2012)High performance IP core for HEVC quantization., , and . ISCAS, page 2828-2831. IEEE, (2015)Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems., , , and . International Journal of Parallel Programming, 41 (2): 236-260 (2013)Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs., , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 745-754. Springer, (2003)