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A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS.

, , , , , , , , , , and . IEEE Symposium on Computer Arithmetic, page 82-86. IEEE Computer Society, (2011)

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A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS., , , , , , , , , and 1 other author(s). IEEE Symposium on Computer Arithmetic, page 82-86. IEEE Computer Society, (2011)Heterogeneous Multi-processor Coherent Interconnect., , , , , , , , , and 12 other author(s). Hot Interconnects, page 17-24. IEEE Computer Society, (2013)A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS., , , , , , , , , and 18 other author(s). VLSI Design, page 286-291. IEEE Computer Society, (2012)Cross-Platform Support for Rapid Development of Mobile Acoustic Sensing Applications., , and . MobiSys, page 455-467. ACM, (2018)A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure., , , , , , , , , and 26 other author(s). ISSCC, page 262-601. IEEE, (2007)Towards cognitive evaluation of computer-drawn sketches., and . The Visual Computer, 17 (4): 236-242 (2001)Fast algorithms for clipping lines and line segments in E2., and . The Visual Computer, 14 (1): 31-38 (1998)SEN State Event Net, Proposal to Enrich the Arsenal of UML Dynamic Diagram.. Software Engineering Research and Practice, page 980-987. CSREA Press, (2006)Microfluidic Injector Simulation With FSAW Sensor for 3-D Integration., , and . IEEE Trans. Instrumentation and Measurement, 64 (4): 849-856 (2015)3D Densely Convolutional Networks for Volumetric Segmentation., , and . CoRR, (2017)