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Disambiguation of "Jabir, Abusaleh M."

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Novel memristive logic architectures.

, , , and . PATMOS, page 196-199. IEEE, (2016)

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M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

M. Christmann

 

Other publications of authors with the same name

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases., , , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 258-269. Springer, (2012)A Galois Field Based Logic Synthesis Approach with Testability., , , , and . VLSI Design, page 629-634. IEEE Computer Society, (2008)On the design of different concurrent EDC schemes for S-Box and GF(p)., , , , and . ISQED, page 211-218. IEEE, (2010)BCH code based multiple bit error correction in finite field multiplier circuits., , , , and . ISQED, page 615-620. IEEE, (2011)A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields., , , and . ECCTD, page 600-603. IEEE, (2011)MODD for CF: a representation for fast evaluation of multiple-output functions., , , and . HLDVT, page 61-66. IEEE Computer Society, (2004)MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions., and . DATE, page 1388-1389. IEEE Computer Society, (2004)Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability., , , and . IET Computers & Digital Techniques, 4 (5): 428-437 (2010)Analytic models for crossbar read operation., , , , and . IOLTS, page 3-4. IEEE, (2016)GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (4): 698-711 (2008)