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High-speed network modeling for full system simulation.

D. Lugones, D. Franco, D. Rexachs, J. Moure, E. Luque, E. Argollo, A. Falcón, D. Ortega, and P. Faraboschi. IISWC, page 24-33. IEEE Computer Society, (2009)

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Juan Vargas University of Stuttgart

C. Traut

C. Honold

Jose Juan Jeronimo Rendon University of Stuttgart

Ph. D. Juan Esteban Martinez Jaramillo University of Stuttgart

Other publications of authors with the same name

Improving the Execution Performance of FreeSurfer - A New Scheduled Pipeline Scheme for Optimizing the Use of CPU and GPU Resources.J. Delgado, J. Moure, Y. Vives-Gilabert, M. Delfino-Reznicek, A. Espinosa, and B. Gómez-Ansón. Neuroinformatics, 12 (3): 413-421 (2014)Graduate students learning strategies through research collaboration.E. Argollo, M. Hanzich, D. Mostaccio, G. Bianchini, P. Fritzsche, F. Bonàs, E. Luque, J. Moure, and D. Rexachs. ITiCSE, page 262. ACM, (2004)A reconfigurable cache memory with heterogeneous banks.D. Benitez, J. Moure, D. Rexachs, and E. Luque. DATE, page 825-830. IEEE, (2010)Strategy of Microscopic Parallelism for Bitplane Image Coding.F. Auli-Llinas, P. Enfedaque, J. Moure, I. Blanes, and V. Sanchez. DCC, page 163-172. IEEE, (2015)Analysis and improvement of map-reduce data distribution in read mapping applications.A. Espinosa, P. Hernández, J. Moure, J. Protasio, and A. Ripoll. The Journal of Supercomputing, 62 (3): 1305-1317 (2012)Performance and Power Evaluation of an Intelligently Adaptive Data Cache.D. Benitez, J. Moure, D. Rexachs, and E. Luque. HiPC, volume 3769 of Lecture Notes in Computer Science, page 363-375. Springer, (2005)Target Encoding for Efficient Indirect Jump Prediction.J. Moure, D. Benitez, D. Rexachs, and E. Luque. Euro-Par, volume 3648 of Lecture Notes in Computer Science, page 497-507. Springer, (2005)Wide and efficient trace prediction using the local trace predictor.J. Moure, D. Benitez, D. Rexachs, and E. Luque. ICS, page 55-65. ACM, (2006)GPU-Accelerated Real-Time Stixel Computation.D. Juárez, A. Espinosa, J. Moure, D. Vázquez, and A. Peña. WACV, page 1054-1062. IEEE Computer Society, (2017)Adaptive L2 Cache for Chip Multiprocessors.D. Benitez, J. Moure, D. Rexachs, and E. Luque. Euro-Par Workshops, volume 4854 of Lecture Notes in Computer Science, page 28-37. Springer, (2007)

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Disambiguation of "Moure, Juan C."

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High-speed network modeling for full system simulation.

Please choose a person to relate this publication to

Juan Vargas University of Stuttgart

C. Traut

C. Honold

Jose Juan Jeronimo Rendon University of Stuttgart

Ph. D. Juan Esteban Martinez Jaramillo University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Moure, Juan C."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML High-speed network modeling for full system simulation.

Please choose a person to relate this publication to

Juan Vargas University of Stuttgart

C. Traut

C. Honold

Jose Juan Jeronimo Rendon University of Stuttgart

Ph. D. Juan Esteban Martinez Jaramillo University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

High-speed network modeling for full system simulation.