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SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits.

, , , , and . HOST, page 31-36. IEEE Computer Society, (2012)

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A Methodology for Rapid Prototyping of Analog Systems., and . ICCD, page 482-488. IEEE Computer Society, (1999)Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis., , , , and . Formal Methods in System Design, 19 (3): 237-273 (2001)Tuning Vth Hopping for Aggressive Runtime Leakage Control., , and . J. Low Power Electronics, 6 (3): 447-456 (2010)Dynamic Characteristics of Power Gating During Mode Transition., , and . IEEE Trans. VLSI Syst., 19 (2): 237-249 (2011)Finite state machine verification on MIMD machines., and . EURO-DAC, page 514-520. IEEE Computer Society Press, (1992)Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems., and . VLSI Signal Processing, 24 (2-3): 181-209 (2000)Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis., and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-20. Springer, (2007)Adaptive Sampling and Modeling of Analog Circuit Performance Parameters., , and . VLSI-SOC, page 142-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Regression based circuit matrix models for accurate performance estimation of analog circuits., and . VLSI-SoC, page 48-53. IEEE, (2007)MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators., and . VLSI-SOC, page 416-421. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)